1. Technical Field
The disclosure relates to a frequency multiplier, and more particularly to an apparatus and a method for multiplying frequency of a clock signal by automatic calibration.
2. Related Art
Over the years, various problems occur as microprocessors become higher in integration and performance. First, the volume increase of the System-on-Chip (SoC) is caused by the increase in clock skew and clock frequency. As a result, the period of one cycle is shortened, thereby increasing the burden of jitter. Second, higher integration requires higher power density, so there is also a need to take a low-power design into consideration.
Therefore, an apparatus which can generate high frequency clock based on multiply frequency method while keeping the low-jitter and low power consumption is in demand.